Lithography, as used in the manufacture of integrated circuits (ICs), involves the process of printing two-dimensional geometric shapes onto the surface of a semiconductor substrate. These shapes make up the parts of the circuit, such as the gate electrodes, contacts, vias, metal interconnects, and so on.
As part of the IC lithographic process, a radiation-sensitive material, such as photoresist, is usually applied to the silicon wafer and dried. The photoresist layer is then exposed using the proper geometrical patterns through a photomask by means of an imaging tool. The imaging tool utilizes some source of light or radiation to expose the mask. After exposure, the wafer is usually soaked in a solution that develops the exposed images in the photoresist. By way of example, these masking patterns provide a way of developing electrical contacts on the silicon substrate.
Quite commonly, the geometries used for fabricating IC devices are rectangular in shape. When printing rectilinear geometries, certain problems arise, particularly at the corner regions of the pattern. For example, during exposure to light or radiation the photoresist integrates energy contributions from all surrounding areas. This means that the exposure dose in one vicinity of the wafer is affected by the exposure dose in neighboring vicinities. This phenomenon is frequently referred to as the proximity effect.
Since a corner region in a photoresist pattern lacks neighboring regions, the exposure dose in a corner will always be less than the exposure dose delivered to the body or to an elongated side of the pattern. As a result, the corners of a developed photoresist pattern will actually be somewhat rounded, rather than square, due to the fact that less energy has been delivered to the corners than to the other areas of the masking pattern. In low density circuits where device geometries are large, corner rounding has a negligible effect on device behavior. However, in very large-scale integrated circuits (VLSI), where device structures are much smaller (e.g., submicron), rounding effects can wreak considerable havoc on the circuit's performance. For instance, rounding of electrical contacts reduces the total area available for conduction, thereby resulting in an increased contact resistance.
Table 1, shown below, illustrates how corner rounding can produce a loss of area in small contacts for a typical semiconductor process. Obviously, it is undesirable for any VLSI circuit to suffer from the detrimental effects of increased contact resistance resulting from a loss of contact area.
TABLE 1 ______________________________________ Actual Feature Actual CD Area Lost During Design CD (in Resist) Printing % Area Loss ______________________________________ 0.60 .mu.m 0.577 .mu.m 0.099 .mu.m.sup.2 27.4% 0.55 .mu.m 0.518 .mu.m 0.092 .mu.m.sup.2 30.4% 0.50 .mu.m 0.371 .mu.m 0.142 .mu.m.sup.2 56.0% 0.45 .mu.m 0.285 .mu.m 0.139 .mu.m.sup.2 68.5% 0.40 .mu.m Not resolved 0.160 .mu.m.sup.2 100% ______________________________________
Another challenging task of the IC lithographic process is to print a two-dimensional feature, such as a contact mask, with feature sizes comparable to, or smaller than, the resolution limit to the imaging tool, Practitioners in the art understand that the resolution of an imaging tool is ordinarily defined as the minimum feature that the exposure tool can repeatedly print onto the wafer. By way of example, the resolution of a commercial imaging tool such as the ASM 5500/60 is around 0.47 microns. This means that as the critical dimensions of the mask features shrink--approaching the resolution limit of the lithographic equipment--the consistency between the mask layout and the actual layout pattern developed in the photoresist is significantly reduced. In fact, beyond a certain dimensional limit, some images are simply unresolvable (see, e.g., Table 1).
FIGS. 1A-1C illustrate this phenomenon. FIG. 1A shows an isolated feature edge illuminated by a light or a radiation source. After the illuminated feature edge is passed through the lense of the associated imaging tool, an image intensity edge gradient is produced on the substrate surface. This aerial edge gradient represents the change in image intensity from the fully illuminated regions to the completely dark or masked regions of the substrate.
FIG. 1B illustrates a feature having two close edges which are exposed simultaneously by an imaging tool. In accordance with the principles discussed above, each edge of the feature produces as its own aerial edge gradient with no diffraction at the edge separation shown. In other words, the adjacent edge gradients are not mixed due to the fact that the feature is completely resolvable by the imaging tool. Note that each edge gradient represents the characteristic of the imaging tool, which can be described by its numerical aperture (NA) and the exposure wavelength (.lambda.) of the source radiation.
When the two feature edges are brought into close proximity during a single exposure, the two edge gradients begin to interact or diffract. At a certain minimum separation (shown in FIG. 1B), the two adjacent edge gradients still maintain their own identity. However, as the two edges are moved closer than the minimum resolvable separation of the imaging tool (as shown in FIG. 1C), diffraction causes a mixture of the edge gradients. The result is that the identity of each individual edge is lost. In other words, the combined aerial edge gradients are simply not resolvable.
The minimum separation that must be maintained in a lithographic process to avoid overlapping of edge gradients is defined by the Rayleigh limit (i.e., the resolution) of the imaging tool. Mathematically, the Rayleigh limit can be expressed as: EQU Rayleigh limit=k(.lambda./NA)
where k is an adjustable parameter dependent upon a variety of processing factors such as resist type. A typical value of k for a semiconductor production process is about 0.7. For a state-of-the-art imaging tool, such as the ASM 5500/60, .lambda.=0.36 microns, NA=0.54, so that the minimum separation of two resolvable edges is approximately 0.47 microns. What this means is that this particular imaging tool is not useful for printing features that have critical dimensions or patterned edges which are spaced narrower than approximately 0.47 microns apart.
Based on the Rayleigh criterion, it is apparent that in order to improve the resolution of photolithographic processes, a new generation of imaging tools may need to be created. These tools would have to achieve higher numerical apertures and/or utilize new exposure sources having much shorter wavelengths. The problem, however, is that such improved imaging tools are not commercially available at present. Moreover, the development of such tools will require substantial investment of capital as well as considerable advances in existing imaging technologies. Alternative techniques such as exposure tuning, contrast enhancement layers, phase shift masking, and E-beam or X-ray technologies are currently either very costly or offer only minimal improvements in the resolution limit.
As will be seen, the present invention discloses a novel method of image decomposition which can be utilized in conjunction with existing imaging tools to radically improve the resolution limit of a lithographic process. The invented method is particularly well-suited for use in printing very small two-dimensional features such as contacts, vias, etc., on a semiconductor wafer. In addition, the invented method relieves the Rayleigh limit when imaging larger feature sizes and produces the desired two-dimensional patterns with much less complicated exposure routines as compared to prior art approaches. The net result is that the present invention markedly improves the overall lithographic process while extending the resolution limit far beyond that which is ordinarily achievable using standard imaging tools and techniques.